Swami Vivekananda University

AARFIVE Designs Pvt. Ltd

NOTICE:

Applications are invited for the six months’ Certificate Course on Introduction to IBM Business Cognos Analytics under the Centre for Artificial Intelligence, Swami Vivekananda University. The course highlights are as follows:

Eligibility: Open to students pursuing Graduation 5th Semester and above
Duration: 24 weeks (6 months)
Hours / week: 01 Hours per day
Mode of Delivery: Hybrid (i.e. both online and on campus)
Assessment: Written Examination and Viva-Voce to be held at the end of the course.
Certification: Participants who successfully complete the course requirements will duly receive a Certificate on Artificial Intelligence from Swami Vivekananda University.
Course Fees: Free

Apply Online

COURSE:

Certificate Course on IBM Cognos Analytics

CONTENT:

This course will cover the foundational aspects of Artificial Intelligence, including theoretical concepts and practical applications. The content is structured to provide a step-by-step understanding of AI, from basic principles to more advanced topics.

Overview of RISC-V

Week 1: Introduction to RISC-V

Overview of RISC-V architecture and its history
Comparison with other ISAs (e.g. x86, ARM)
RISC-V design goals and benefits
Basic components of RISC-V architecture: registers, ALU, and memory

Week 2: RISC-V Instruction Set

RISC-V base integer instructions (RV32I, RV64I)
Formats and encoding of RISC-V instructions
Addressing modes and immediate values
Control and status registers

Week 3: RISC-V Extensions

Overview of standard extensions (e.g. M, A, F, D, Q)
Implementing and utilizing extension instructions
Custom extensions and their applications
Practical exercises with RISC-V extensions

Week 4: RISC-V Assembly Language Programming

Writing and understanding RISC-V assembly code
Using simulators and emulators for assembly code testing
Debugging techniques for RISC-V assembly programs
Hands-on assembly language programming exercises

Week 5: RISC-V Microarchitecture and Design

Overview of RISC-V core microarchitecture
Pipeline design and hazards
Branch prediction and cache design
Implementation of RISC-V cores: single-cycle, multi-cycle, and pipelined designs

Week 6: RISC-V Toolchain and Development Environment

Introduction to RISC-V development tools (e.g. GCC, LLVM)
Setting up a RISC-V development environment
Cross-compilation and linking for RISC-V
Using RISC-V simulators and debuggers (e.g. Spike, QEMU)

Week 7: Advanced Topics and Applications

RISC-V in embedded systems and IoT devices
Performance optimization techniques for RISC-V
Security features and considerations in RISC-V design
Case studies of RISC-V in industry applications

Week 8: Final Project and Review

Project work: designing and implementing a RISC-V based system or application
Presentation of final projects and peer review
Course review and summary
Certification examination and feedback

MISSION:

To equip participants with a thorough understanding of the RISC-V instruction set architecture, enabling them to design, implement, and optimize RISC-V-based systems. The course aims to bridge the gap between theoretical knowledge and practical application, fostering innovation in computer architecture and embedded systems.

VISION:

To be a leading educational program in RISC-V architecture, recognized for its excellence in teaching, hands-on training, and contribution to advancing the field of computer engineering. We aspire to create a community of skilled professionals who drive the future of open-source hardware and processor design.

OBJECTIVES:

Comprehensive Understanding:
- Provide a deep understanding of the RISC-V ISA, including its core principles, instruction formats, and architectural features.
- Explore the design goals and benefits of RISC-V compared to other ISAs.
Hands-On Experience:
- Offer practical training in designing, implementing, and debugging RISC-V processors.
- Develop proficiency with RISC-V tools, simulators, and development environments.
Skill Development:
- Teach participants to write and optimize RISC-V assembly language programs.
- Enable students to apply RISC-V architecture principles in real-world scenarios and embedded systems.
Innovation and Application:
- Encourage innovative use of RISC-V in various applications, from embedded systems to advanced computing systems.
- Provide opportunities to work on projects that demonstrate the practical applications of RISC-V.
Professional Growth:
- Prepare participants for careers in computer architecture, embedded systems, and related fields.
- Support professional development through a strong focus on industry-relevant skills and knowledge.
Collaboration and Community:
- Foster a collaborative learning environment where students can engage with peers, instructors, and industry professionals.
- Build a network of RISC-V enthusiasts and experts who contribute to the advancement of open-source hardware.

DURATION:

The entire course shall be of 03 (Three) months’ duration.

ELIGIBILITY CRITERIA:

Any B.Tech Students who are currently pursuing their final year or pre-final year (are also eligible to apply).

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